Impacts of high-k gate dielectrics and low temperature on the performance of nanoscale CNTFETs, ISSN 1569-8025

Citation:

Djamil, Rechem, et al. 2016. “Impacts of high-k gate dielectrics and low temperature on the performance of nanoscale CNTFETs, ISSN 1569-8025”. Journal of Computational Electronics Volume 15 : pp 1308-1315.

Abstract:

The influence of gate dielectric materials on the performance of a carbon nanotube field-effect transistor has been studied by a numerical simulation model. This model is based on a two-dimensional nonequilibrium Green’s function formalism performed with the self-consistent solution of the Poisson and Schrödinger equations. The device performance is investigated in terms of leakage current, on-state current, ION/IOFF" id="MathJax-Element-1-Frame" role="presentation" style="position:relative;" tabindex="0">ION/IOFF current ratio, subthreshold slope, drain-induced barrier lowering, as well as transconductance, drain conductance, and intrinsic gate delay. This study is carried out over a wide range of dielectric permittivities at low temperatures ranging from room temperature down to 100 K.

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