Abstract:

In this paper, channel doping engineering aspect is proposed as a new way to improve the junctionless Gate All Around (GAA) MOSFET performance for digital and analog applications. The amended channel doping consists of a lateral graded profile, where the channel is divided into two regions with different doping levels. Analytical approaches for the drain current, leakage power, digital and small signal parameters are developed incorporating the impact of graded channel doping (GCD) paradigm on the device electrical behavior. Exhaustive study based on a performance comparison between the proposed structure and the conventional one is carried out, where the proposed design exhibits a good capability in improving the overall device figures-of-merit (FoMs), governing the leakage and the analog performance. More importantly, Particle Swarm Optimization (PSO) approach is proposed as a metaheuristic technique to boost the device performance through carefully adjusting the design parameters of the proposed GCD feature. It is found that the optimized design outperforms considerably the conventional counterpart and enable making wise trade-offs, where an enhancement of 300% in the I _ON /I _OFF ratio, 482% in the intrinsic gain, and 340% in the cut-off frequency has been reached. Besides, the proposed design provides a sufficient capability for suppression of the leakage effects. The obtained results underline the distinctive property of the proposed design for bridging the gap between high analog and digital performances with ultra-low power consumption. This makes the proposed design a potential alternative for ultra-low power and high electrical performance applications.

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