<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>17</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Abdelmalek Nidhal</style></author><author><style face="normal" font="default" size="100%">Djeffal Fayçal</style></author><author><style face="normal" font="default" size="100%">Bentrcia Toufik</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">Continuous semianalytical modeling of vertical surrounding-gate tunnel FET: analog/RF performance evaluation, ISSN 1569-8025</style></title><secondary-title><style face="normal" font="default" size="100%">Journal of Computational Electronics</style></secondary-title></titles><dates><year><style  face="normal" font="default" size="100%">2018</style></year></dates><urls><web-urls><url><style face="normal" font="default" size="100%">https://link.springer.com/article/10.1007/s10825-018-1141-9</style></url></web-urls></urls><volume><style face="normal" font="default" size="100%">Vloume. 17</style></volume><pages><style face="normal" font="default" size="100%">pp 724-735</style></pages><language><style face="normal" font="default" size="100%">eng</style></language><abstract><style face="normal" font="default" size="100%">A continuous and accurate model based on the two-dimensional (2D) potential solution of a tunnel field-effect transistor (TFET) with undoped vertical surrounding-gate (VSG) structure is proposed. Both ambipolarity and dual modulation effects are included to obtain a more accurate analytical model, whose validity is demonstrated by comparison with two-dimensional numerical simulations using ATLAS-2D. The continuity of the proposed model enables extraction of analog/radiofrequency (RF) parameters and device figures of merit. Moreover, the effect of introducing a high-&lt;span class=&quot;InlineEquation&quot; id=&quot;IEq1&quot;&gt;&lt;span class=&quot;MathJax&quot; data-mathml=&quot;&lt;math xmlns=&amp;quot;http://www.w3.org/1998/Math/MathML&amp;quot;&gt;&lt;mi&gt;&amp;amp;#x03BA;&lt;/mi&gt;&lt;/math&gt;&quot; id=&quot;MathJax-Element-1-Frame&quot; role=&quot;presentation&quot; style=&quot;position:relative;&quot; tabindex=&quot;0&quot;&gt;&lt;nobr aria-hidden=&quot;true&quot;&gt;&lt;span class=&quot;math&quot; id=&quot;MathJax-Span-1&quot; style=&quot;width:0.639em;display:inline-block;&quot;&gt;&lt;span style=&quot;display:inline-block;position:relative;width:0.583em;height:0px;111%;&quot;&gt;&lt;span style=&quot;position:absolute;clip:rect(1.625em,1000.56em,2.396em,-1000em);top:-2.226em;left:0em;&quot;&gt;&lt;span class=&quot;mrow&quot; id=&quot;MathJax-Span-2&quot;&gt;&lt;span class=&quot;mi&quot; id=&quot;MathJax-Span-3&quot; style=&quot;MathJax_Math;font-style:italic;&quot;&gt;κ&lt;/span&gt;&lt;/span&gt;&lt;/span&gt;&lt;/span&gt;&lt;/span&gt;&lt;/nobr&gt;&lt;/span&gt;&lt;/span&gt; layer on the gate oxide in improving the behavior of the VSG-TFET is explored for use in high-performance analog/RF applications. The proposed continuous analytical model can be easily implemented in commercial simulators to study and investigate VSG-TFET-based nanoelectronic circuits.</style></abstract><issue><style face="normal" font="default" size="100%"> Issue 2</style></issue></record></records></xml>